研究者情報 - 和田　康孝

ワダ　ヤスタカ WADA Yasutaka
和田　康孝

所属明治学院大学情報数理学部情報数理学科

職種教授

展覧会・演奏会・競技会等
2005/02	Multigrain parallel processing on compiler cooperative chip multiprocessor (IEEE Proc. of the 9th Annual Workshop on Interaction between Compilers and Computer Architectures)
2005/10	Compiler Control Power Saving Scheme for Multi Core Processors (Proc. of The 18th International Workshop on Languages and Compilers for Parallel Computing)
2006/01	Parallelizing Compilation Scheme for Reduction of Power Consumption of Chip Multiprocessors (Proc. of the 12th International Workshop on Compilers for Parallel Computers (CPC2006))
2006/04	Performance Evaluation of Heterogeneous Chip Multi-Processor with MP3 Audio Encoder (IEEE Proc. of The IEEE Symposium on Low-Power and High Speed Chips (COOL Chips IX))
2006/05	マルチコアプロセッサにおけるコンパイラ制御低消費電力化手法 (先進的計算基盤システムシンポジウム論文集（SACSIS 2006）)
2006/07	Performance Evaluation of Compiler Controlled Power Saving Scheme (Proc. of International Workshop on Advanced Low Power Systems (ALPS2006))
2007/06	Heterogeneous Multiprocessor on a Chip Which Enables 54x AAC-LC Stereo Encoding (IEEE Proc. of The 2007 IEEE Symposium on VLSI Circuits)
2008/03	Software-cooperative power-efficient heterogeneous multi-core for media processing (IEEE Proc. of 13th Asia and South Pacific Design Automation Conference (ASP-DAC 2008))
2008/06	Parallelizing Compiler Cooperative Heterogeneous Multicore (Proc. of Workshop on Software and Hardware Challenges of Manycore Platforms (SHCMP 2008))
2008/12	Parallelization with Automatic Parallelizing Compiler Generating Consumer Electronics Multicore API (IEEE Proc. of The 2008 International Symposium on Parallel and Distributed Processing with Applications)
2009/01	Performance of OSCAR Multigrain Parallelizing Compiler on Multicore Processors (Proc. of the 14th Workshop on Compilers for Parallel Computing (CPC 2009))
2010/02	A 45nm 37.3GOPS/W heterogeneous multi-core SoC (IEEE 2010 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC2010))
2010/04	A 45nm Heterogeneous Multi-core SoC Supporting an over 32-bits Physical Address Space for Digital Appliance (IEEE Proc. of IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XIII))
2011/10	Efficient Parallel Implementations of Controlled Optimization of Traffic Phases (Springer Berlin Heidelberg Proc. of The 11th International Conference on Algorithms and Architectures for Parallel Processing)
2011/10	Parallelizing Compiler Framework and API for Power Reduction and Software Productivity of Real-time Heterogeneous Multicores (Proc. of The 23rd International Workshop on Languages and Compilers for Parallel Computing)
2012/01	OSCAR Parallelizing Compiler and API for Real-time Low Power Heterogeneous Multicores (Proc. of The 16th Workshop on Compilers for Parallel Computing (CPC 2012))
2013/05	マルチコア・プロセッサ向けのヘルパースレッドによるキャッシュ制御支援手法の提案 (情報処理学会先進的計算基盤システムシンポジウム論文集（SACSIS2013）)
2013/09	A Scalable Multiplier for Arbitrary Large Numbers Supporting Homomorphic Encryption (IEEE Proc. of The 16th Euromicro Conference on Digital System Design (DSD 2013))
2015/05	HPCアプリケーションの消費電力最適化に向けた性能・消費電力情報の統合手法 (情報処理学会 2015年ハイパフォーマンスコンピューティングと計算科学シンポジウム論文集（HPCS2015）)
2015/09	Coarse Grain Task Parallelization of Earthquake Simulator GMS Using OSCAR Compiler on Various cc-NUMA Servers (Proc. of The 28th International Workshop on Languages and Compilers for Parallel Computing)
2015/11	Analyzing and Mitigating the Impact of Manufacturing Variability in Power-Constrained Supercomputing (Proc. of SC15)
2018/03	A Power Management Framework with Simple DSL for Automatic Power-Performance Optimization on Power-Constrained HPC Systems (Springer Supercomputing Frontiers Asia 2018 (SCFA 2018))
2020/11	次世代先端的計算基盤に関する白書
2021/11	Mitigating Process Variations with Cooperative Tuning for Performance and Power through a Simple DSL (2021 Ninth International Symposium on Computing and Networking Workshops (CANDARW))
2022/05	Performance Evaluation of Data Transfer API for Rank Level Approximate Computing on HPC Systems (2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW))