研究者情報 - 和田　康孝

ワダ　ヤスタカ WADA Yasutaka
和田　康孝

所属明治学院大学情報数理学部情報数理学科

職種教授

著書・論文歴
論文	Enabling Dynamic Approximate Computing for HPC Applications Journal of Information Processing 33,668-674頁 (共著) 2025/10/15
論文	Ideal Parametrisation Estimation for Variational Quantum Circuit Classifiers Using Machine Learning Proc. of 2024 IEEE International Conference on Quantum Computing and Engineering (QCE2024) 2,114-119頁 (共著) 2024/09
論文	Data Transfer API and its Performance Model for Rank-Level Approximate Computing on HPC Systems International Journal of Networking and Computing 13 (1),48-61頁 (共著) 2023/01
論文	Performance Evaluation of Data Transfer API for Rank Level Approximate Computing on HPC Systems 2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW),445-448頁 (共著) 2022/05
論文	Mitigating Process Variations with Cooperative Tuning for Performance and Power through a Simple DSL 2021 Ninth International Symposium on Computing and Networking Workshops (CANDARW) (共著) 2021/11
論文	Secure Image Inference using Pairwise Activation Functions IEEE Access 9,118271-118290頁 (共著) 2021/08
論文	Efficient and Precise Profiling, Modeling and Management on Power and Performance for Power Constrained HPC Systems IEICE Transactions on Electronics E104-C (6),237-246頁 (共著) 2021/06
論文	Deep Learning Acceleration with a Look-Up-Table Based Memory Logic Conjugated System Transactions of The Japan Institute of Electronics Packaging 12,E18-008-1-E18-008-7頁 (共著) 2019/06
論文	A Power Management Framework with Simple DSL for Automatic Power-Performance Optimization on Power-Constrained HPC Systems Supercomputing Frontiers Asia 2018 (SCFA 2018) LNCS 10776 (共著) 2018/03
論文	Analyzing and Mitigating the Impact of Manufacturing Variability in Power-Constrained Supercomputing Proc. of SC15 (共著) 2015/11
論文	Multigrain parallel processing on compiler cooperative chip multiprocessor Proc. of the 9th Annual Workshop on Interaction between Compilers and Computer Architectures,11-20頁 (共著) 2005/02
その他	次世代先端的計算基盤に関する白書 (共著) 2020/11